Reduction of Power and Delay in Shift Register using MTCMOS Technique
Reduction of Power and Delay in Shift Register using MTCMOS Technique
Diptaa 
Abstract:
In the process of large scale integration lot of transistors are implemented in a very minimum area. Combinational logic has very useful in quantum and many industrial designs. Reducing the power and delay is the principle object in VLSI design. Suppressing sub-threshold leakage current in large scale integration is essential for achieving green computing and facilitating the more usage of power electronics. In this paper the shift register is implemented with or without MTCMOS technique. The Cosmos Scope tool is used to analyze the power delay with the simulation in HSPICE. The Shift Register is fabricated by using the 32nm and 45nm BPTM model file. With the help of MTCMOS technique in Shift Register a reduction in leakage power is 44% in 32nm with the applied voltage of 0.7V and 57% in 45nm with the applied voltage of 0.9V. Energy is reduced by the 5% for 0.7V for 32nm and 21 % for 0.9V at 45nm.
