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A High-Throughput Architecture of List Successive Cancellation Polar Codes Decoder with Large List S

A High-Throughput Architecture of List Successive Cancellation Polar Codes Decoder with Large List Size

ABSTRACT :

As the first kind of forward error correction (FEC) codes that achieve channel capacity, polar codes have attracted much research interest recently. Compared with other popular FEC codes, polar codes decoded by list successive cancellation decoding (LSCD) with a large list size have better error correction performance. However, due to the serial decoding nature of LSCD and the high complexity of list management (LM), the decoding latency is high, which limits the usage of polar codes in practical applications that require low latency and high throughput. In this work, we study the high-throughput implementation of LSCD with a large list size. Specifically, at the algorithmic level, to achieve a low decoding latency with moderate hardware complexity, two decoding schemes, a multi-bit double thresholding scheme and a partial G-node look-ahead scheme, are proposed. Then, a high-throughput VLSI architecture implementing the proposed algorithms is developed with optimizations on different computation modules. From the implementation results on UMC 90 nm CMOS technology, the proposed architecture achieves decoding throughputs of 1.103 Gbps, 977 Mbps and 827 Mbps when the list sizes are 8, 16 and 32, respectively.

 

EXISTING SYSTEM :

The delay and complexity of the programmable PE is mainly brought by the adders and the critical path includes only one stage of adder and some multiplexers, which is highlighted with the dashed.

We compare the proposed programmable PE structure with the existing ones from the literatures and the results.

All the PE structures listed here use sign-magnitude representation for the LLR operands. The PE structure in uses one fewer adder than ours; however, this is at the cost of larger logic delay. Moreover, it cannot support the GLAH calculation.

 

PROPOSED SYSTEM :

The algorithmic level, to achieve a low decoding latency with moderate hardware complexity, two decoding schemes, a multi-bit double thresholding scheme and a partial G-node look-ahead scheme, are proposed.

A  high-throughput VLSI architecture implementing the proposed algorithms is developed with optimizations on different computation modules.

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